1. Field of the Invention
The present invention relates to a voltage controller, and more particularly, to a voltage controller implemented in a low operation voltage device.
2. Description of the Prior Art
Generally, an operating voltage of a low operation voltage device is smaller than a potential provided by an external power supply. Therefore, a voltage dropping circuit is designed to drop the potential of the external power supply to an allowable operating voltage range of the low operation voltage device. However, an input voltage and current provided to the low operation voltage device when the low operation voltage device is idle is smaller than that when the low operation voltage device is operating. Thus, the voltage dropping circuit must be designed to properly drop voltages according these different conditions.
When the low operation voltage device, taking a static random access memory (SRAM) for example, writes data or reads data, it requires a larger operating voltage. However, some rules of a memory specification indicate that the current flowing into the SRAM must be limited when the SRAM is idle. In this condition, the SRAM just needs a smaller voltage that is large enough to keep all the data stored in the memory. Therefore, when the SRAM is idle, the voltage dropping circuit can drop the potential of the external power supply to a much smaller voltage, and then provide the smaller voltage to the SRAM to keep the data. Since the SRAM requires a basic voltage to maintain data, when the SRAM is idle, it has to detect whether the received operating voltage is smaller than the basic voltage so as to prevent data stored in the memory from becoming inaccurate.
Please refer to FIG. 1, which shows a voltage controller 1 and a low operation voltage device 2 according to the prior art. The voltage controller 1 comprises a first transistor 12 and a second transistor 14, wherein a threshold voltage HV of the first transistor 12 is larger than a threshold voltage LV of the first transistor 14. The voltage controller 1 drops the potential of an external power supply VCC via the first transistor 12 or the second transistor 14, and the dropped voltage is provided to the low operation voltage device 2.
A drain of the first transistor 12 and a drain of the second transistor 14 are both coupled to the external power supply VCC, such as a battery; a source of the first transistor 12 and a source of the second transistor 14 are both coupled to a voltage input of the low operation voltage device 2; a gate of the first transistor 12 receives an idle signal STBY of the low operation voltage device 2; and a gate of the second transistor 14 receives an operating signal ACT of the low operation voltage device 2.
When the low operation voltage device 2 is operating, the operating signal ACT is high while the idle signal STBY is low, resulting in turning on the second transistor 14 and turning off the first transistor 12. The potential of the external power supply VCC is dropped by the second transistor 14, and thereby provides the voltage of (VCC−LV) to the low operation voltage device 2. On the contrary, when the low operation voltage device 2 is idle, the operating signal ACT is low while the idle signal STBY is high, resulting in turning off the second transistor 14 and turning on the first transistor 12. The potential of the external power supply VCC is dropped by the first transistor 12 with larger threshold voltage, and only provides the voltage of (VCC−HV) to the low operation voltage device 2. Thus, the prior art can drop different voltages according to different conditions.
However, the voltage controller 1 of the prior art has some disadvantages. Suppose that the low operation voltage device 2 is an SRAM with a 2-volt operating voltage when reading and writing data and a 0.8-volt basis operating voltage to maintain data, the external power supply is a battery with a maximum 3.6-volt voltage, the threshold voltage HV of the first transistor 12 is 1.2 volts, and the threshold voltage LV of the second transistor 14 is 0.7 volts.
If the low operation voltage device 2 switches from the idle status to the operation status, the input voltage power path of the low operation voltage device 2 must be switched. That is, the input voltage originally provided from the first transistor 12 should be provided from the second transistor 14 instead. Since the low operation voltage device 2 is a memory capable of reading and writing data, if the input voltage provided to the low operation voltage device 2 were not immediately increased from low potential to high potential, it might fail in reading or writing the first data bit.
For example, please refer to FIG. 2 and FIG. 3, which respectively show the low operation voltage device 2 idle and operating when the external power supply VCC is 2.7 volts. As shown in FIG. 2, when the low operation voltage device 2 is idle, the first transistor 12 drops the potential of the external power supply VCC down to 1.5 volts to be provided to the low operation voltage device 2. As shown in FIG. 3, when the low operation voltage device 2 is operating, the second transistor 14 drops the potential of the external power supply VCC down to 2 volts to be provided to the low operation voltage device 2. Therefore, the input voltage of the low operation voltage device 2 must be increased from 1.5 volts to 2 volts when transferring from the idle status to the operation status. The time for switching the power path might result in failing to read or store the first data bit.
The other possible way to fail to read or store the first data bit is as follows. Please refer to FIG. 4, which shows the low operation voltage device 2 idle when the potential of the external power supply is decreased to 2 volts. At this time, the low operation voltage device 2 receives the operating voltage of 0.8 volts, where the data stored in the memory can still be kept precisely. If the potential of the external power supply VCC is smaller than 2 volts, the data cannot be maintained precisely anymore. If reading or writing data is executed, the battery must be changed or be charged. Please refer to FIG. 5, which shows the potential of the external power supply VCC of FIG. 4 increased from 2 volts to 3.6 volts and the operation status entered. At this time, the input voltage of the low operation voltage device 2 is increased from 0.8 volts to 2.9 volts, which still requires a time to switch the power path, resulting in failing to read or store the first data bit.
In addition, please refer to FIG. 6, which shows the low operation voltage device 2 idle when the potential of the external power supply VCC is 3.6 volts. Since some rules of the memory specification limit the flowing current of the idle status, in FIG. 6, the low operation voltage device 2 receives 2.4 volts, which does not conform to the rules. If the threshold voltage of the first transistor 12 is increased to reduce the input current, when the first transistor 12 with increased threshold voltage is in the status of FIG. 4, the data cannot be stored precisely because the input voltage of the low operation voltage device 2 is smaller than 0.8 volts. Thus, adjusting the threshold voltages of the voltage controller 1 of the prior art would limit the applications.